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30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance
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Title
30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance
Issued Date
2024-02-21
Citation
Spetalnick, Samuel D. (2024-02-21). 30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance. International Solid-State Circuits Conference, 482–484. doi: 10.1109/ISSCC49657.2024.10454500
Type
Conference Paper
ISBN
9798350306200
ISSN
2376-8606
Abstract
Tiny surveillance robots need to efficiently compute a perception front-end workload, consisting of a neural network inference stack, and a localization back-end workload implementing a set of state-space equations. Miniaturization and low-power actuation make bristle robots [1] attractive locomotion platforms, but size limits lead to stringent energy constraints. The edge accelerator needs low leakage for long retentive stretches and efficient matrix compute for active bursts. We present a 0.84TOPS/W, 110μW retentive-sleep-capable resistive random-access memory (RRAM)-based accelerator in 40nm with 10 very long instruction word (VLIW)-controlled nonvolatile memory (NVM) matrix units (NMUs) with, in total, 5MB of RRAM, combined with a 10T SRAM-based state-update accelerator enabled by in-place memory updates. At VMIN, the design improves NVM access energy to 0.256pJ/b and peak NVM bandwidth to 12.8GB/s. © 2024 IEEE.
URI
http://hdl.handle.net/20.500.11750/57830
DOI
10.1109/ISSCC49657.2024.10454500
Publisher
IEEE Solid-State Circuits Society
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윤종혁
Yoon, Jong-Hyeok윤종혁

Department of Electrical Engineering and Computer Science

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