Cited time in webofscience Cited time in scopus

An Antiphase-synchronized Dual Ring Oscillator Based Capacitive Voltage Doubler with Power Optimizable Feedback Loop

An Antiphase-synchronized Dual Ring Oscillator Based Capacitive Voltage Doubler with Power Optimizable Feedback Loop
Alternative Title
전력 최적화가 가능한 되먹임 폐회로가 있는 역 위상 동기화 듀얼 링 발진기 기반 축전기 방식 승압 회로
Yeonjae Shin
DGIST Authors
Yeonjae ShinJunghyup LeeJaeha Kung
Jaeha Kung
Issued Date
Awarded Date
Low-ripple, Charge pump, Capacitive voltage doubler, clockless, power optimization, 낮은 리플, 자가 발진, 되먹임, 전력 효율, 역 위상 동기화
This thesis proposed an antiphase-synchronized dual ring oscillator based voltage doubler with power optimizable feedback loop. This voltage doubler is suitable for wearable IoT devices that use battery power in terms of power efficiency and area. The antiphase-synchronization with two ring oscillator makes the output voltage ripple smaller which is inevitable in ring oscillator based voltage doubler due to its phase mismatch. Minimizing such ripple can reduce energy and area consumption by eliminating the need for an additional ripple reduction circuit. Besides, the power efficiency will be optimized by the digital feedback loop. It detects the output voltage and tunes the frequency according to the equation about the relationship between the output voltage and power efficiency. This chip is fabricated in the 180nm CMOS process and occupies 0.086$\text{mm}^2$. It achieves 79\% power efficiency within the load current 35 - 90 $\mu A$. It is not the best power efficiency compared to other state-of-the-art circuits. However, it is not suitable for a one-to-one comparison with other circuits that needs external blocks such as LDO for ripple reduction, clock, and supply voltage for the feedback loop.
Table Of Contents
I. Introduction 1
1.1 Background 1
1.1.1 Types of PMIC 2
1.2 Key Specifications of DC-DC Converters 4
1.2.1 Voltage Conversion Efficiency 4
1.2.2 Power Efficiency 5
1.2.3 Output Voltage Ripple 7
1.2.4 Start-up time 8
II.Literature Review 9
2.1 Dickson Voltage Multiplier 9
2.2 Cross-coupled Voltage doubler 11
2.3 Self-oscillating voltage doubler 12
2.3.1 Self-oscillating 12
2.3.2 Feedback topology 14
III.Proposed System 17
3.1 System Design 17
3.1.1 Antiphase-synchronized two single-ended stacked ring structure 18
3.1.2 Feedback blocks 19
3.2 Circuit design 20
3.2.1 Delay cell 20
3.2.2 Phase synchronizing block 21
3.2.3 Latched comparator 22
3.2.4 Charge pump 23
IV.Measurement Results and Conclusions 24
4.1 Measurement Results 24
4.2 Conclusions 32
References 33
Information and Communication Engineering
Related Researcher
  • 이정협 Lee, Junghyup 전기전자컴퓨터공학과
  • Research Interests Analog and Mixed Signal IC Design; Smart Sensor Systems; Bio-medical ICs and Body Channel Communication Systems
Files in This Item:


기타 데이터 / 3.74 MB / Adobe PDF download
Appears in Collections:
Department of Electrical Engineering and Computer Science Theses Master


  • twitter
  • facebook
  • mendeley

Items in Repository are protected by copyright, with all rights reserved, unless otherwise indicated.