Full metadata record
DC Field | Value | Language |
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dc.contributor.author | Yoon, Jong-Hyeok | - |
dc.contributor.author | Chang, Muya | - |
dc.contributor.author | Khwa, Win-San | - |
dc.contributor.author | Chih, Yu-Der | - |
dc.contributor.author | Chang, Meng-Fan | - |
dc.contributor.author | Raychowdhury, Arijit | - |
dc.date.accessioned | 2022-10-25T03:00:01Z | - |
dc.date.available | 2022-10-25T03:00:01Z | - |
dc.date.created | 2022-02-16 | - |
dc.date.issued | 2022-03 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/20.500.11750/16924 | - |
dc.description.abstract | Computing-in-memory (CIM) architectures have paved the way for energy-efficient artificial intelligence (AI) systems while outperforming von Neumann architectures. In particular, resistive RAM (RRAM)-based CIM has drawn attention due to high cell density, non-volatility, and compatibility with a CMOS process. RRAM also exhibits the feasibility of high-capacity CIM with multi-bit encoding per cell exploiting an appropriate on/off resistance ratio. However, the prior work regarding multi-level RRAM cells mainly focused on achieving higher bit resolution in write without consideration of CIM performance. Thus, the circuit solution to achieve multi-bit encoding per cell dedicated to RRAM-based CIM (RCIM) is of importance to support high-capacity AI systems with reliable CIM performance. This article presents a 256 x 256 CIM multi-level RRAM macro featuring iterative write with verification to achieve reliable multi-bit encoding per cell and the voltage-sensing readout circuit to surmount the underlying logic ambiguity in RCIM architectures. In addition, we also demonstrate the key design space of a fabricated RRAM array in the write operation with extensive experiments. The test chip fabricated in a Taiwan Semiconductor Manufacturing Company (TSMC) 40-nm CMOS and RRAM process achieves a peak energy efficiency of 118.44 TOPS/W in the ternary-weight multiply-and-accumulate (MAC) operation and demonstrates the feasibility of multi-level RCIM with voltage-sensing RCIM. IEEE | - |
dc.language | English | - |
dc.publisher | Institute of Electrical and Electronics Engineers | - |
dc.title | A 40-nm 118.44-TOPS/W Voltage-Sensing Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/JSSC.2022.3141370 | - |
dc.identifier.wosid | 000750384300001 | - |
dc.identifier.scopusid | 2-s2.0-85123726794 | - |
dc.identifier.bibliographicCitation | IEEE Journal of Solid-State Circuits, v.57, no.3, pp.845 - 857 | - |
dc.description.isOpenAccess | FALSE | - |
dc.subject.keywordAuthor | multiply-and-accumulate (MAC) | - |
dc.subject.keywordAuthor | processing-in-memory | - |
dc.subject.keywordAuthor | resistive RAM (RRAM) | - |
dc.subject.keywordAuthor | write verification | - |
dc.subject.keywordAuthor | Computer architecture | - |
dc.subject.keywordAuthor | Microprocessors | - |
dc.subject.keywordAuthor | Resistance | - |
dc.subject.keywordAuthor | Encoding | - |
dc.subject.keywordAuthor | Common Information Model (computing) | - |
dc.subject.keywordAuthor | Artificial intelligence | - |
dc.subject.keywordAuthor | Random access memory | - |
dc.subject.keywordAuthor | Computing-in-memory (CIM) | - |
dc.subject.keywordAuthor | convolutional neural network | - |
dc.subject.keywordAuthor | multi-level cell | - |
dc.subject.keywordPlus | ACCELERATOR | - |
dc.subject.keywordPlus | PROCESSOR | - |
dc.citation.endPage | 857 | - |
dc.citation.number | 3 | - |
dc.citation.startPage | 845 | - |
dc.citation.title | IEEE Journal of Solid-State Circuits | - |
dc.citation.volume | 57 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.type.docType | Article | - |
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