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dc.contributor.author Kang, Jaeyoung -
dc.contributor.author Khaleghi, Behnam -
dc.contributor.author Kim, Yeseong -
dc.contributor.author Rosing, Tajana -
dc.date.accessioned 2023-12-26T18:14:25Z -
dc.date.available 2023-12-26T18:14:25Z -
dc.date.created 2022-03-28 -
dc.date.issued 2022-01-18 -
dc.identifier.isbn 9781665421355 -
dc.identifier.uri http://hdl.handle.net/20.500.11750/46873 -
dc.description.abstract Hyperdimensional Computing (HDC) is an emerging lightweight machine learning method alternative to deep learning. One of its key strengths is the ability to accelerate it in hardware, as it offers massive parallelisms. Prior work primarily focused on FPGA and ASIC, which do not provide the seamless flexibility required for HDC applications. Few studies that attempted GPU designs are inefficient, partly due to the complexity of accelerating HDC on GPUs because of the bit-level operations of HDC. Besides, HDC training exhibited low hardware utilization due to sequential operations. In this paper, we present XCelHD, a high-performance GPU-powered framework for HDC. XCelHD uses a novel training method to maximize the training speed of the HDC model while fully utilizing hardware. We propose memory optimization strategies specialized for GPU-based HDC, minimizing the access time to different memory subsystems and redundant operations. We show that the proposed training method reduces the required number of training epochs by four-fold to achieve comparable accuracy. Our evaluation results on NVIDIA Jetson TX2 show that XCelHD is up to 35× faster than the state-of-the-art TensorFlow-based HDC implementation. © 2022 IEEE. -
dc.language English -
dc.publisher Institute of Electrical and Electronics Engineers Inc. -
dc.title XCelHD: An Efficient GPU-Powered Hyperdimensional Computing with Parallelized Training -
dc.type Conference Paper -
dc.identifier.doi 10.1109/ASP-DAC52403.2022.9712549 -
dc.identifier.scopusid 2-s2.0-85126104434 -
dc.identifier.bibliographicCitation 27th Asia and South Pacific Design Automation Conference, ASP-DAC 2022, pp.220 - 225 -
dc.identifier.url https://tsys.jp/aspdac/2022/program/program_abst.html#3C-2 -
dc.citation.conferencePlace CH -
dc.citation.conferencePlace Virtual -
dc.citation.endPage 225 -
dc.citation.startPage 220 -
dc.citation.title 27th Asia and South Pacific Design Automation Conference, ASP-DAC 2022 -
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Department of Electrical Engineering and Computer Science Computation Efficient Learning Lab. 2. Conference Papers

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