Abstract List of Contents I. Introduction II. Background and Motivation 2.1. Tiered Memory System 2.2. Demand Paging and Page Fault 2.3. Performance Impact of Slow Memory 2.4. Effective Page Management Through Monitor III. Related Work 3.1. NUMA Hint Fault 3.2. PEBS: Processor Event-Based Sampling 3.3. Page Table-Based IV. Page Scan Acceleration by Dynamically Eliminating Page Table Walk 4.1. Challenges 4.1.1. Migration 4.1.2. De-allocation 4.1.3. Allocation 4.2. Main Architecture 4.2.1. Physical Memory Address List Initialization 4.2.2. Access Pattern Monitoring 4.2.3. Thresholds of Page Fault Tracking and Synchronization 4.2.4. Page Fault Tracking 4.2.5. Synchronize V. Evaluation 5.1. Experimental Methodology 5.2. Performance with Monitoring 5.2.1. Monitoring Overhead 5.2.2. Page Fault Tracking Overhead 5.2.3. Application Performance 5.3. Threshold Optimization 5.3.1. Page Fault Threshold 5.3.2. Synchronization Threshold and Time Window 5.3.3. Number of Untracked Pages to Tolerate 5.4. Effect of LRU and LFU 5.5. Comparison with PEBS 5.6. Overhead of Physical Memory Address List VI. Conclusion References 요약문
