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Simultaneous Enhancement of Performance and Stability in Dual-Gate a-IGZO Thin-Film Transistors via Single-Step Laser Annealing for Capacitor-Less DRAM
- Department of Electrical Engineering and Computer Science
- Advanced Electronic Devices Research Group(AEDRG) - Kwon Lab.
- 1. Journal Articles
- Department of Electrical Engineering and Computer Science
- Advanced Electronic Devices Research Group(AEDRG) - Jang Lab.
- 1. Journal Articles
- Department of Electrical Engineering and Computer Science
- Advanced Electronic Devices Research Group(AEDRG) - Lee Lab.
- 1. Journal Articles
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- Title
- Simultaneous Enhancement of Performance and Stability in Dual-Gate a-IGZO Thin-Film Transistors via Single-Step Laser Annealing for Capacitor-Less DRAM
- Issued Date
- 2026-10
- Citation
- ADVANCED FUNCTIONAL MATERIALS, v.36, no.84
- Type
- Article
- Author Keywords
- DRAM ; dual-gate thin-film transistor ; IGZO ; laser annealing ; amorphous oxide semiconductors
- Keywords
- COMPACT MODEL ; TEMPERATURE ; BIAS ; HYDROGEN ; DENSITY ; CHANNEL ; DESIGN ; OXYGEN ; RANDOM-ACCESS MEMORY
- ISSN
- 1616-301X
- Abstract
-
Wide-bandgap amorphous oxide semiconductors (AOSs), particularly indium-gallium-zinc-oxide (IGZO), offer ultralow off-current and back-end-of-line compatibility, making them attractive for advanced dynamic random access memory (DRAM). In capacitor-less two-transistor (2T0C) DRAM, dual-gate (DG) a-IGZO TFTs are promising read transistors, but achieving a stable positive threshold voltage (V-th) typically reduces field-effect mobility (& micro;(FE)) and increases contact resistance (R-C), limiting fast operation. This study introduces a spatially selective laser annealing strategy that overcomes this limitation in a single step. The steep thermal gradient promotes oxygen incorporation at the top-gate dielectric/channel interface, passivating defects without severely depleting carrier density. Simultaneously, WOx interlayer removal combined with oxygen redistribution forms conductive n(+) regions at source/drain contacts. This dual modification stabilizes the channel and reduces R-C, enabling both high & micro;(FE) (37.9 cm(2) V-1 s(-1)) and a stable positive V-th (0.27 V). The optimized devices exhibit small Delta V-th under bias stress and reliable operation, demonstrating the read function of 2T0C DRAM, maintaining stable "0/1" state discrimination and wide memory windows (>10(5)) for over 10 000 s. This single-step process provides a practical route to overcome the performance-stability trade-off in AOS TFTs, highlighting strong potential for emerging memory applications.
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- Publisher
- WILEY-V C H VERLAG GMBH
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Related Researcher
- Lee, Byeongmoon이병문
-
Department of Electrical Engineering and Computer Science
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