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A 1-v 4.6-mw/channel fully differential neural recording front-end ic with current-controlled pseudoresistor in 0.18-mm cmos
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Title
A 1-v 4.6-mw/channel fully differential neural recording front-end ic with current-controlled pseudoresistor in 0.18-mm cmos
DGIST Authors
Lee, Junghyup
Issued Date
2019-02
Citation
Lee, Taeju. (2019-02). A 1-v 4.6-mw/channel fully differential neural recording front-end ic with current-controlled pseudoresistor in 0.18-mm cmos. doi: 10.5573/JSTS.2019.19.1.030
Type
Article
Article Type
Article
Author Keywords
Current-reuseFully differential front-endLow-noise amplifierLow-powerNeural recordingNoise efficiency factorBiomedical deviceCurrent-controlled pseudoresistor
Keywords
CMOS integrated circuitsCutoff frequencyDifferential amplifiersEfficiencyEnergy efficiencyNeurophysiologyNoise efficiency factorsLow noise amplifiersAnalog to digital conversionVariable gain amplifiersVoltage regulatorsBiomedical devicesCurrent reuseFront endLow PowerNeural recordings
ISSN
1598-1657
Abstract
This paper presents a fully differential implantable neural recording front-end IC for monitoring neural activities. Each analog front-end (AFE) consists of a low-noise amplifier (LNA), a variable gain amplifier (VGA), and a buffer. The output signal of the AFE is digitized through a successive approximation register analog-to-digital converter (SAR ADC). The LNA adopts the current-reuse technique to improve the current efficiency, achieving the power consumption as low as 0.95 mW. The implemented LNA has the gain of 40 dB, the low-pass cutoff frequency of 10 kHz, and the high-pass cutoff frequency of sub-1 Hz which is realized using the current-controlled pseudoresistor. The VGA controls the gain from 21.9 dB to 33.9 dB for efficient digitization while consuming the power of 0.35 mW. The buffer drives the capacitive DAC of the ADC and consumes the power of 3.28 mW. The fabricated AFE occupies the area of 0.11 mm 2 /Channel and consumes 4.6 mW/Channel under 1-V supply voltage. Each channel achieves the input-referred noise of 2.88 mV rms , the NEF of 2.38, and the NEF 2 V DD of 5.67. The front-end IC is implemented in a standard 1P6M 0.18-mm CMOS process. © 2019, Institute of Electronics Engineers of Korea. All rights reserved.
URI
http://hdl.handle.net/20.500.11750/9826
DOI
10.5573/JSTS.2019.19.1.030
Publisher
Institute of Electronics Engineers of Korea
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이정협
Lee, Junghyup이정협

Department of Electrical Engineering and Computer Science

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