Full metadata record
DC Field | Value | Language |
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dc.contributor.author | Yoon, Jong-Hyeok | - |
dc.contributor.author | Chang, Muya | - |
dc.contributor.author | Khwa, Win-San | - |
dc.contributor.author | Chih, Yu-Der | - |
dc.contributor.author | Chang, Meng-Fan | - |
dc.contributor.author | Raychowdhury, Arijit | - |
dc.date.accessioned | 2022-01-11T11:30:14Z | - |
dc.date.available | 2022-01-11T11:30:14Z | - |
dc.date.created | 2021-11-27 | - |
dc.date.issued | 2022-01 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/20.500.11750/16080 | - |
dc.description.abstract | Computing-in-memory (CIM) architectures have gained importance in achieving high-throughput energy-efficient artificial intelligence (AI) systems. Resistive RAM (RRAM) is a promising candidate for CIM architectures due to a multiply-and-accumulate (MAC)-friendly structure, high bit density, compatibility with a CMOS process, and nonvolatility. Notwithstanding the advancement of RRAM technology, the reliability of an RRAM array hinders the spread of RRAM applications such that a circuit-technology joint approach is necessary to attain reliable RRAM-based CIM architectures. This article presents a 64-kb hybrid CIM/digital RRAM macro supporting: 1) active-feedback-based voltage-sensing read (RD) to enable 1-8-b programmable vector-matrix multiplication under a low-resistance ratio of the high-resistance state to the low-resistance state in an RRAM array; 2) iterative write with verification to secure a tight resistance distribution; and 3) online RD-disturb detection in the background during CIM. The test chip fabricated in a 40-nm CMOS and RRAM process achieves a peak energy efficiency of 56.67 TOPS/W while demonstrating the eight-bitline hybrid CIM/digital MAC operation with 1-8-b inputs and weights and 20-b outputs without quantization. © 1966-2012 IEEE. | - |
dc.language | English | - |
dc.publisher | Institute of Electrical and Electronics Engineers | - |
dc.title | A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/jssc.2021.3101209 | - |
dc.identifier.wosid | 000732363400001 | - |
dc.identifier.scopusid | 2-s2.0-85122288288 | - |
dc.identifier.bibliographicCitation | IEEE Journal of Solid-State Circuits, v.57, no.1, pp.68 - 79 | - |
dc.description.isOpenAccess | FALSE | - |
dc.subject.keywordAuthor | Computing-in-memory (CIM) | - |
dc.subject.keywordAuthor | convolutional neural network (CNN) | - |
dc.subject.keywordAuthor | multiply-and-accumulate (MAC) | - |
dc.subject.keywordAuthor | processing-in-memory | - |
dc.subject.keywordAuthor | read (RD) disturb | - |
dc.subject.keywordAuthor | resistive RAM (RRAM) | - |
dc.subject.keywordAuthor | write (WR) verification. | - |
dc.subject.keywordPlus | Computer architecture | - |
dc.subject.keywordPlus | Resistance | - |
dc.subject.keywordPlus | Reliability | - |
dc.subject.keywordPlus | Artificial intelligence | - |
dc.subject.keywordPlus | Phase change random access memory | - |
dc.subject.keywordPlus | Integrated circuit reliability | - |
dc.subject.keywordPlus | Current control | - |
dc.citation.endPage | 79 | - |
dc.citation.number | 1 | - |
dc.citation.startPage | 68 | - |
dc.citation.title | IEEE Journal of Solid-State Circuits | - |
dc.citation.volume | 57 | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.relation.journalResearchArea | Engineering | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.type.docType | Article | - |
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