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BitS-Net: Bit-Sparse Deep Neural Network for Energy-Efficient RRAM-Based Compute-In-Memory
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dc.contributor.author Karimzadeh, Foroozan -
dc.contributor.author Yoon, Jong-Hyeok -
dc.contributor.author Raychowdhury, Arijit -
dc.date.accessioned 2022-07-06T02:33:20Z -
dc.date.available 2022-07-06T02:33:20Z -
dc.date.created 2022-02-17 -
dc.date.issued 2022-05 -
dc.identifier.issn 1549-8328 -
dc.identifier.uri http://hdl.handle.net/20.500.11750/16497 -
dc.description.abstract The rising popularity of intelligent mobile devices and the computational cost of deep learning-based models call for efficient and accurate on-device inference schemes. We propose a novel model compression scheme that allows inference to be carried out using bit-level sparsity, which can be efficiently implemented using in-memory computing macros. In this paper, we introduce a method called BitS-Net to leverage the benefits of bit-sparsity (where the number of zeros are more than number of ones in binary representation of weight/activation values) when applied to compute-in-memory (CIM) with resistive RAM (RRAM) to develop energy efficient DNN accelerators operating in the inference mode. We demonstrate that BitS-Net improves the energy efficiency by up to 5x for ResNet models on the ImageNet dataset. -
dc.language English -
dc.publisher Institute of Electrical and Electronics Engineers -
dc.title BitS-Net: Bit-Sparse Deep Neural Network for Energy-Efficient RRAM-Based Compute-In-Memory -
dc.type Article -
dc.identifier.doi 10.1109/TCSI.2022.3145687 -
dc.identifier.wosid 000751480600001 -
dc.identifier.scopusid 2-s2.0-85124224751 -
dc.identifier.bibliographicCitation Karimzadeh, Foroozan. (2022-05). BitS-Net: Bit-Sparse Deep Neural Network for Energy-Efficient RRAM-Based Compute-In-Memory. IEEE Transactions on Circuits and Systems I: Regular Papers, 69(5), 1952–1961. doi: 10.1109/TCSI.2022.3145687 -
dc.description.isOpenAccess FALSE -
dc.subject.keywordAuthor Deep neural network -
dc.subject.keywordAuthor quantization -
dc.subject.keywordAuthor in memory computing -
dc.subject.keywordAuthor DNN accelerator -
dc.citation.endPage 1961 -
dc.citation.number 5 -
dc.citation.startPage 1952 -
dc.citation.title IEEE Transactions on Circuits and Systems I: Regular Papers -
dc.citation.volume 69 -
dc.description.journalRegisteredClass scie -
dc.description.journalRegisteredClass scopus -
dc.relation.journalResearchArea Engineering -
dc.relation.journalWebOfScienceCategory Engineering, Electrical & Electronic -
dc.type.docType Article -
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윤종혁
Yoon, Jong-Hyeok윤종혁

Department of Electrical Engineering and Computer Science

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