Cited time in webofscience Cited time in scopus

Full metadata record

DC Field Value Language
dc.contributor.author Hwang, Sangwoo -
dc.contributor.author Hwang, Yujin -
dc.contributor.author Kim, Duhee -
dc.contributor.author Lee, Junhee -
dc.contributor.author Choe, Han Kyoung -
dc.contributor.author Lee, Junghyup -
dc.contributor.author Kang, Hongki -
dc.contributor.author Kung, Jaeha -
dc.date.accessioned 2024-01-30T01:10:14Z -
dc.date.available 2024-01-30T01:10:14Z -
dc.date.created 2023-09-12 -
dc.date.issued 2023-08 -
dc.identifier.issn 1662-453X -
dc.identifier.uri http://hdl.handle.net/20.500.11750/47694 -
dc.description.abstract Recent developments in artificial neural networks and their learning algorithms have enabled new research directions in computer vision, language modeling, and neuroscience. Among various neural network algorithms, spiking neural networks (SNNs) are well-suited for understanding the behavior of biological neural circuits. In this work, we propose to guide the training of a sparse SNN in order to replace a sub-region of a cultured hippocampal network with limited hardware resources. To verify our approach with a realistic experimental setup, we record spikes of cultured hippocampal neurons with a microelectrode array (in vitro). The main focus of this work is to dynamically cut unimportant synapses during SNN training on the fly so that the model can be realized on resource-constrained hardware, e.g., implantable devices. To do so, we adopt a simple STDP learning rule to easily select important synapses that impact the quality of spike timing learning. By combining the STDP rule with online supervised learning, we can precisely predict the spike pattern of the cultured network in real-time. The reduction in the model complexity, i.e., the reduced number of connections, significantly reduces the required hardware resources, which is crucial in developing an implantable chip for the treatment of neurological disorders. In addition to the new learning algorithm, we prototype a sparse SNN hardware on a small FPGA with pipelined execution and parallel computing to verify the possibility of real-time replacement. As a result, we can replace a sub-region of the biological neural circuit within 22 μs using 2.5 × fewer hardware resources, i.e., by allowing 80% sparsity in the SNN model, compared to the fully-connected SNN model. With energy-efficient algorithms and hardware, this work presents an essential step toward real-time neuroprosthetic computation. Copyright © 2023 Hwang, Hwang, Kim, Lee, Choe, Lee, Kang and Kung. -
dc.language English -
dc.publisher Frontiers -
dc.title ReplaceNet: real-time replacement of a biological neural circuit with a hardware-assisted spiking neural network -
dc.type Article -
dc.identifier.doi 10.3389/fnins.2023.1161592 -
dc.identifier.scopusid 2-s2.0-85168676939 -
dc.identifier.bibliographicCitation Frontiers in Neuroscience, v.17 -
dc.description.isOpenAccess TRUE -
dc.subject.keywordAuthor brain-chip interface -
dc.subject.keywordAuthor dynamic synapses -
dc.subject.keywordAuthor hardware implementation -
dc.subject.keywordAuthor spiking neural network -
dc.subject.keywordAuthor online learning -
dc.subject.keywordPlus DEPENDENT SYNAPTIC PLASTICITY -
dc.subject.keywordPlus LEARNING ALGORITHM -
dc.subject.keywordPlus MODEL -
dc.citation.title Frontiers in Neuroscience -
dc.citation.volume 17 -

qrcode

  • twitter
  • facebook
  • mendeley

Items in Repository are protected by copyright, with all rights reserved, unless otherwise indicated.

BROWSE