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  Department of Electrical Engineering and Computer Science Intelligent Integrated Circuits and Systems Lab

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Article
Design and Analysis of ΔΣ Modulator Analogous Bang-Bang Digital PLL
  • ACCEPT
  • Park, Minsu. Design and Analysis of ΔΣ Modulator Analogous Bang-Bang Digital PLL. International Journal of Circuit Theory and Applications. doi: 10.1002/cta.70013
  • Wiley
  • View : 245
  • Download : 0

Hexagonal metal complex based mechanically robust transparent ultrathin gold μECoG for electro-optical neural interfaces

Article
Hexagonal metal complex based mechanically robust transparent ultrathin gold μECoG for electro-optical neural interfaces
  • Kim, Duhee ; 
  • Bissannagari, Murali ; 
  • Kim, Boil ; 
  • Hong, Nari ; 
  • Park, Jaeu ; 
  • Lim, Hyeongtae ; 
  • Lee, Junhee ; 
  • Lee, Jungha ; 
  • Kim, Yoon Kyoung ; 
  • Cho, Youngjae ; 
    • et al
  • 2025-04
  • npj Flexible Electronics, v.9, no.1
  • Nature Publishing Group
  • View : 508
  • Download : 6
Article
BEE-SLAM: A 65-nm 17.96-TOPS/W Location-Sharing-Based Multi-Agent Neuromorphic SLAM Accelerator for Swarm Robotics
  • 2025-03
  • Lee, Jaehyun. (2025-03). BEE-SLAM: A 65-nm 17.96-TOPS/W Location-Sharing-Based Multi-Agent Neuromorphic SLAM Accelerator for Swarm Robotics. IEEE Journal of Solid-State Circuits, 60(3), 963–976. doi: 10.1109/JSSC.2024.3505960
  • Institute of Electrical and Electronics Engineers
  • View : 137
  • Download : 0
Article
A Discrete Multitone Wireline Transceiver Datapath With On-Chip Sign-Sign LMS Adaptation And Loading Profile Optimization On RFSoC
  • Lee, Jaewon ; 
  • Jang, Seoyoung ; 
  • Kim, Donggeon ; 
  • Choi, Yujin ; 
  • Yoon, Jong-Hyeok ; 
  • Braendli, Matthias ; 
  • Morf, Thomas ; 
  • Kossel, Marcel ; 
  • Francese, Pier-Andrea ; 
  • Kim, Gain
  • 2024-12
  • Lee, Jaewon. (2024-12). A Discrete Multitone Wireline Transceiver Datapath With On-Chip Sign-Sign LMS Adaptation And Loading Profile Optimization On RFSoC. IEEE Transactions on Circuits and Systems II: Express Briefs, 71(12), 4889–4893. doi: 10.1109/TCSII.2024.3450695
  • Institute of Electrical and Electronics Engineers Inc.
  • View : 95
  • Download : 0
Article
An Edge Accelerator With 5 MB of 0.256-pJ/bit Embedded RRAM and a Localization Solver for Bristle Robot Surveillance
  • Spetalnick, Samuel D. ; 
  • Lele, Ashwin Sanjay ; 
  • Crafton, Brian ; 
  • Chang, Muya ; 
  • Ryu, Sigang ; 
  • Yoon, Jong-Hyeok ; 
  • Hao, Zhijian ; 
  • Ansari, Azadeh ; 
  • Khwa, Win-San ; 
  • Chih, Yu-Der ; 
    • et al
  • 2025-01
  • Spetalnick, Samuel D. (2025-01). An Edge Accelerator With 5 MB of 0.256-pJ/bit Embedded RRAM and a Localization Solver for Bristle Robot Surveillance. IEEE Journal of Solid-State Circuits, 60(1), 35–48. doi: 10.1109/JSSC.2024.3457676
  • Institute of Electrical and Electronics Engineers
  • View : 98
  • Download : 0
Article
A Dual-Precision and Low-Power CNN Inference Engine Using a Heterogeneous Processing-in-Memory Architecture
  • Jung, Sangwoo ; 
  • Lee, Jaehyun ; 
  • Park, Dahoon ; 
  • Lee, Youngjoo ; 
  • Yoon, Jong-Hyeok ; 
  • Kung, Jaeha
  • 2024-12
  • Jung, Sangwoo. (2024-12). A Dual-Precision and Low-Power CNN Inference Engine Using a Heterogeneous Processing-in-Memory Architecture. IEEE Transactions on Circuits and Systems I: Regular Papers, 71(12), 5546–5559. doi: 10.1109/TCSI.2024.3395842
  • Institute of Electrical and Electronics Engineers
  • View : 191
  • Download : 0
Article
A 40-nm 118.44-TOPS/W Voltage-Sensing Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding
  • Yoon, Jong-Hyeok ; 
  • Chang, Muya ; 
  • Khwa, Win-San ; 
  • Chih, Yu-Der ; 
  • Chang, Meng-Fan ; 
  • Raychowdhury, Arijit
  • 2022-03
  • Yoon, Jong-Hyeok. (2022-03). A 40-nm 118.44-TOPS/W Voltage-Sensing Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding. IEEE Journal of Solid-State Circuits, 57(3), 845–857. doi: 10.1109/JSSC.2022.3141370
  • Institute of Electrical and Electronics Engineers
  • View : 320
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Article
BitS-Net: Bit-Sparse Deep Neural Network for Energy-Efficient RRAM-Based Compute-In-Memory
  • 2022-05
  • Karimzadeh, Foroozan. (2022-05). BitS-Net: Bit-Sparse Deep Neural Network for Energy-Efficient RRAM-Based Compute-In-Memory. IEEE Transactions on Circuits and Systems I: Regular Papers, 69(5), 1952–1961. doi: 10.1109/TCSI.2022.3145687
  • Institute of Electrical and Electronics Engineers
  • View : 311
  • Download : 0
Article
A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection
  • Yoon, Jong-Hyeok ; 
  • Chang, Muya ; 
  • Khwa, Win-San ; 
  • Chih, Yu-Der ; 
  • Chang, Meng-Fan ; 
  • Raychowdhury, Arijit
  • 2022-01
  • Yoon, Jong-Hyeok. (2022-01). A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection. IEEE Journal of Solid-State Circuits, 57(1), 68–79. doi: 10.1109/jssc.2021.3101209
  • Institute of Electrical and Electronics Engineers
  • View : 504
  • Download : 0
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